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    公开号:NL2007481A
    申请号:NL2007481
    申请日:2011-09-27
    公开日:2012-04-02
    发明作者:Timothy J Millet；Eric P Machnicki；Deniz Balkan；Vijay Gupta
    申请人:Apple Inc；
    IPC主号:
    专利说明:

    Hardware Dynamic Cache Power Management BACKGROUNDField of the Invention
    [0001] This invention is related to the field of digital systems and, more particularly, topower management in digital systems.
    Description of the Related Art
    [0002] As the number of transistors included on an integrated circuit "chip" continuesto increase, power management in the integrated circuits continues to increase inimportance. Power management can be critical to integrated circuits that are includedin mobile devices such as personal digital assistants (PDAs), cell phones, smart phones,laptop computers, net top computers, etc. These mobile devices often rely on batterypower, and reducing power consumption in the integrated circuits can increase the lifeof the battery. Additionally, reducing power consumption can reduce the heatgenerated by the integrated circuit, which can reduce cooling requirements in thedevice that includes the integrated circuit (whether or not it is relying on batterypower).
    [0003] Clock gating is often used to reduce dynamic power consumption in anintegrated circuit, disabling the clock to idle circuitry and thus preventing switching inthe idle circuitry. Some integrated circuits have implemented power gating in additionto clock gating. With power gating, the power to ground path of the idle circuitry isinterrupted, reducing the leakage current to near zero. When the power is gated to ablock and later restored, the block can require reinitialization. The reinitialization ishandled by software executed on a processor in the system.
    SUMMARY
    [0004] In an embodiment, a control circuit is configured to transmit operations to acircuit block that is being powered up after being powered down, to reinitialize thecircuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled, and software executing in the systemthat includes the control circuit and circuit block may program the memory with theoperations at a time prior to the powering down of the circuit block. In an embodiment,the control circuit may also be configured to transmit other operations from thememory to the circuit block prior to the circuit block being powered down.
    Accordingly, the circuit block may be powered up or powered down even during timesthat the processors in the system are powered down (and thus software is notexecutable at the time), without waking the processors for the power up/power downevent.
    [0005] In an embodiment, the circuit block may be a cache coupled to the one or moreprocessors, and the control circuit may be part of a bridge that couples one or moreperipherals and/or peripheral interface controllers to the cache. The cache may bepowered down if the processors are powered down and the peripherals are idle (at leastwith respect to accessing memory) for a period of time. The cache may be powered upfor a peripheral memory operation or to power up the processors. In one embodiment,the cache control circuitry may be powered down, but the cache memory may remainpowered to retain the cache blocks that are stored in the cache.
    BRIEF DESCRIPTION OF THE DRAWINGS
    [0006] The following detailed description makes reference to the accompanyingdrawings, which are now briefly described.
    [0007] Fig. 1 is a block diagram of one embodiment of a system.
    [0008] Fig. 2 is a block diagram of a portion of the system shown in Fig. 1, in greaterdetail for an embodiment.
    [0009] Fig. 3 is a flowchart illustrating operation of one embodiment of a powermanager to power down a cache dynamically.
    [0010] Fig. 4 is a flowchart illustrating operation of one embodiment of a core interfaceunit to power down a cache dynamically.
    [0011] Fig. 5 is a flowchart illustrating operation of one embodiment of a powermanager to power up a cache dynamically.
    [0012] Fig. 6 is a flowchart illustrating operation of one embodiment of a core interfaceunit to power up a cache dynamically.
    [0013] Fig. 7 is a timing diagram illustrating dynamic power down and power up of acache.
    [0014] Fig. 8 is a flowchart illustrating operation of one embodiment of cacheconfiguration code.
    [0015] Fig. 9 is a block diagram of a computer accessible storage medium.
    [0016] Fig. 10 is a block diagram of another embodiment of a system.
    [0017] While the invention is susceptible to various modifications and alternativeforms, specific embodiments thereof are shown by way of example in the drawings andwill herein be described in detail. It should be understood, however, that the drawingsand detailed description thereto are not intended to limit the invention to the particularform disclosed, but on the contrary, the intention is to cover all modifications,equivalents and alternatives falling within the spirit and scope of the present inventionas defined by the appended claims. The headings used herein are for organizationalpurposes only and are not meant to be used to limit the scope of the description. Asused throughout this application, the word "may" is used in a permissive sense (i.e.,meaning having the potential to), rather than the mandatory sense (i.e., meaning must).Similarly, the words "include", "including", and "includes" mean including, but notlimited to.
    [0018] Various units, circuits, or other components may be described as "configuredto" perform a task or tasks. In such contexts, "configured to" is a broad recitation ofstructure generally meaning "having circuitry that" performs the task or tasks duringoperation. As such, the unit/circuit/component can be configured to perform the taskeven when the unit/circuit/component is not currently on. In general, the circuitry thatforms the structure corresponding to "configured to" may include hardware circuitsand/or memory storing program instructions executable to implement the operation.
    The memory can include volatile memory such as static or dynamic random accessmemory and/or nonvolatile memory such as optical or magnetic disk storage, flashmemory, programmable read-only memories, etc. Similarly, variousunits/circuits/components may be described as performing a task or tasks, forconvenience in the description. Such descriptions should be interpreted as includingthe phrase "configured to." Reciting a unit/circuit/component that is configured toperform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112,paragraph six interpretation for that unit/circuit/component.
    DETAILED DESCRIPTION OF EMBODIMENTS
    [0019] An exemplary system and integrated circuit are described below in which alevel 2 (L2) cache may be powered up or down while the processors are powereddown, and control circuitry in a bridge may be configured to perform operations toinitialize the cache at power up and/or to prepare the cache for power down. However,other embodiments may implement a similar mechanism to power up/power down anycircuit block during times that the processors in the system are powered down. Theoperations may be configuration register write operations, as discussed below for theL2 cache, or may be other types of operations such as register read operations orcommands that are interpreted by the circuit block to change the circuit block's state forpower up/power down.
    [0020] Generally, a circuit block may include a set of related circuits that implementone or more identifiable functions. The related circuits may be referred to as logiccircuits or logic circuitry, since the circuits may implement logic operations on inputsto generate outputs. Because the circuits in a given circuit block are related, they may be powered up or powered down as a unit. Each circuit block may generally be treatedas a unit during the design of the integrated circuit (e.g. being physically placed withinthe integrated circuit as a unit). The circuit block may further include memory circuitry(e.g. various static random access memories, or SRAMs) and other storage devices thatare part of the logic circuitry. For example, in an integrated circuit that implements asystem on a chip (SOC), the components of the SOC may each be a separate circuitblock.
    Overview
    [0021] Turning now to Fig. 1, a block diagram of one embodiment of a system 5 isshown. In the embodiment of Fig. 1, the system 5 includes an integrated circuit (IC) 10coupled to external memories 12A-12B. In the illustrated embodiment, the integratedcircuit 10 includes a central processor unit (CPU) block 14 which includes one or moreprocessors 16 and a level 2 (F2) cache 18. Other embodiments may not include F2cache 18 and/or may include additional levels of cache. Additionally, embodimentsthat include more than two processors 16 and that include only one processor 16 arecontemplated. The integrated circuit 10 further includes a set of one or more non-realtime (NRT) peripherals 20 and a set of one or more real time (RT) peripherals 22. Inthe illustrated embodiment, the CPU block 14 is coupled to a bridge/direct memoryaccess (DMA) controller 30, which may be coupled to one or more peripheral devices32A-32C and/or one or more peripheral interface controllers 34. The number ofperipheral devices 32 and peripheral interface controllers 34 may vary from zero to anydesired number in various embodiments. The system 5 illustrated in Fig. 1 furtherincludes a graphics unit 36 comprising one or more graphics controllers such as GO38A and G1 38B. The number of graphics controllers per graphics unit and the numberof graphics units may vary in other embodiments. As illustrated in Fig. 1, the system 5includes a memory controller 40 coupled to one or more memory physical interfacecircuits (PHYs) 42A-42B. The memory PHYs 42A-42B are configured tocommunicate on pins of the integrated circuit 10 to the memories 12A-12B. Thememory controller 40 also includes a set of ports 44A-44E. The ports 44A-44B arecoupled to the graphics controllers 38A-38B, respectively. The CPU block 14 iscoupled to the port 44C. The NRT peripherals 20 and the RT peripherals 22 arecoupled to the ports 44D-44E, respectively. The number of ports included in a memory controller 40 may be varied in other embodiments, as may the number of memorycontrollers. That is, there may be more or fewer ports than those shown in Fig. 1. Thenumber of memory PHYs 42A-42B and corresponding memories 12A-12B may be oneor more than two in other embodiments.
    [0022] Generally, a port may be a communication point on the memory controller 40 tocommunicate with one or more sources. In some cases, the port may be dedicated to asource (e.g. the ports 44A-44B may be dedicated to the graphics controllers 38A-38B,respectively). In other cases, the port may be shared among multiple sources (e.g. theprocessors 16 may share the CPU port 44C, the NRT peripherals 20 may share theNRT port 44D, and the RT peripherals 22 may share the RT port 44E). Each port 44A-44E is coupled to an interface to communicate with its respective agent. The interfacemay be any type of communication medium (e.g. a bus, a point-to-point interconnect,etc.) and may implement any protocol. The interconnect between the memorycontroller and sources may also include any other desired interconnect such as meshes,network on a chip fabrics, shared buses, point-to-point interconnects, etc.
    [0023] The processors 16 may implement any instruction set architecture, and may beconfigured to execute instructions defined in that instruction set architecture. Theprocessors 16 may employ any microarchitecture, including scalar, superscalar,pipelined, superpipelined, out of order, in order, speculative, non-speculative, etc., orcombinations thereof. The processors 16 may include circuitry, and optionally mayimplement microcoding techniques. The processors 16 may include one or more level1 caches, and thus the cache 18 is an L2 cache. Other embodiments may includemultiple levels of caches in the processors 16, and the cache 18 may be the next leveldown in the hierarchy. The cache 18 may employ any size and any configuration (setassociative, direct mapped, etc.).
    [0024] The graphics controllers 38A-38B may be any graphics processing circuitry.Generally, the graphics controllers 38A-38B may be configured to render objects to bedisplayed into a frame buffer. The graphics controllers 38A-38B may include graphicsprocessors that may execute graphics software to perform a part or all of the graphicsoperation, and/or hardware acceleration of certain graphics operations. The amount of hardware acceleration and software implementation may vary from embodiment toembodiment.
    [0025] The NRT peripherals 20 may include any non-real time peripherals that, forperformance and/or bandwidth reasons, are provided independent access to the memory12A-12B. That is, access by the NRT peripherals 20 is independent of the CPU block14, and may proceed in parallel with CPU block memory operations. Other peripheralssuch as the peripherals 32A-32C and/or peripherals coupled to a peripheral interfacecontrolled by the peripheral interface controller 34 may also be non-real timeperipherals, but may not require independent access to memory. Various embodimentsof the NRT peripherals 20 may include video encoders and decoders, scaler circuitryand image compression and/or decompression circuitry, etc.
    [0026] The RT peripherals 22 may include any peripherals that have real timerequirements for memory latency. For example, the RT peripherals may include animage processor and one or more display pipes. The display pipes may includecircuitry to fetch one or more frames and to blend the frames to create a display image.The display pipes may further include one or more video pipelines. The result of thedisplay pipes may be a stream of pixels to be displayed on the display screen. Thepixel values may be transmitted to a display controller for display on the display screen.The image processor may receive camera data and process the data to an image to bestored in memory.
    [0027] The bridge/DMA controller 30 may comprise circuitry to bridge theperipheral(s) 32 and the peripheral interface controller(s) 34 to the memory space. Inthe illustrated embodiment, the bridge/DMA controller 30 may bridge the memoryoperations from the peripherals/peripheral interface controllers through the CPU block14 to the memory controller 40. The CPU block 14 may also maintain coherencebetween the bridged memory operations and memory operations from the processors16/L2 Cache 18. The L2 cache 18 may also arbitrate the bridged memory operationswith memory operations from the processors 16 to be transmitted on the CPU interfaceto the CPU port 44C. The bridge/DMA controller 30 may also provide DMA operationon behalf of the peripherals 32 and the peripheral interface controllers 34 to transfer blocks of data to and from memory. More particularly, the DMA controller may beconfigured to perform transfers to and from the memory 12A-12B through the memorycontroller 40 on behalf of the peripherals 32 and the peripheral interface controllers 34.The DMA controller may be programmable by the processors 16 to perform the DMAoperations. For example, the DMA controller may be programmable via descriptors.The descriptors may be data structures stored in the memory 12A-12B that describeDMA transfers (e.g. source and destination addresses, size, etc.). Alternatively, theDMA controller may be programmable via registers in the DMA controller (notshown).
    [0028] The peripherals 32A-32C may include any desired input/output devices or otherhardware devices that are included on the integrated circuit 10. For example, theperipherals 32A-32C may include networking peripherals such as one or morenetworking media access controllers (MAC) such as an Ethernet MAC or a wirelessfidelity (WiFi) controller. An audio unit including various audio processing devicesmay be included in the peripherals 32A-32C. One or more digital signal processorsmay be included in the peripherals 32A-32C. The peripherals 32A-32C may includeany other desired functional such as timers, an on-chip secrets memory, an encryptionengine, etc., or any combination thereof.
    [0029] The peripheral interface controllers 34 may include any controllers for any typeof peripheral interface. For example, the peripheral interface controllers may includevarious interface controllers such as a universal serial bus (USB) controller, aperipheral component interconnect express (PCIe) controller, a flash memory interface,general purpose input/output (I/O) pins, etc.
    [0030] The memories 12A-12B may be any type of memory, such as dynamic randomaccess memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR,DDR2, DDR3, etc.) SDRAM (including mobile versions of the SDRAMs such asmDDR3, etc., and/or low power versions of the SDRAMs such as LPDDR2, etc.),RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memorydevices may be coupled onto a circuit board to form memory modules such as singleinline memory modules (SIMMs), dual inline memory modules (DIMMs), etc.
    Alternatively, the devices may be mounted with the integrated circuit 10 in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip moduleconfiguration.
    [0031] The memory PHYs 42A-42B may handle the low-level physical interface to thememory 12A-12B. For example, the memory PHYs 42A-42B may be responsible forthe timing of the signals, for proper clocking to synchronous DRAM memory, etc. Inone embodiment, the memory PHYs 42A-42B may be configured to lock to a clocksupplied within the integrated circuit 10 and may be configured to generate a clockused by the memory 12.
    [0032] It is noted that other embodiments may include other combinations ofcomponents, including subsets or supersets of the components shown in Fig. 1 and/orother components. While one instance of a given component may be shown in Fig. 1,other embodiments may include one or more instances of the given component.Similarly, throughout this detailed description, one or more instances of a givencomponent may be included even if only one is shown, and/or embodiments thatinclude only one instance may be used even if multiple instances are shown.
    L2 Cache Power Up/Power Down
    [0033] Turning now to Fig. 2, a block diagram of one embodiment of a portion of theintegrated circuit 10 is shown in greater detail. Particularly, the CPU block 14 and thebridge/DMA controller 30 are shown along with a power manager 50. The CPU block14 includes the processors 16 and the L2 cache 18. In the embodiment of Fig. 2, the L2cache 18 is illustrated as the L2 cache control 18A and the L2 cache memory 18B. TheL2 cache control 18A may include a cache control circuit 52 and a coherence controlcircuit 54. Each of the cache control circuit 52 and the coherence control circuit 54may include configuration registers such as configuration registers 56A-56D. Theprocessors 16 are coupled to the L2 cache control 18A, and more particularly to thecoherence control circuit 54. The coherence control circuit 54 may be coupled to thecache control circuit 52. The L2 cache control 18A, and more particularly the cachecontrol circuit 52, may be coupled to the L2 cache memory 18B. The L2 cache control18A may further be coupled the memory controller 40 (e.g. the CPU port 44C in Fig.
    1). The power manager 50 may be coupled to the L2 cache control 18A (e.g. the L2power control signals in Fig. 2) and the processors 16 (e.g. the processor power controlsignals in Fig. 2).
    [0034] The bridge/DMA controller 30 may include a coherent I/O interface unit (CIF)58, a power up/power down memory 60, and a DMA controller 62. The CIF 58 iscoupled to the power up/power down memory 60, to the DMA controller 62, to the L2cache control 18A (and more particularly to the coherence control circuit 54), to thepower manager 50 (e.g. via the I/O idle, PwrUpReq, and PwrUpAck signals in Fig. 2),and to the peripherals 32A-32C and/or the peripheral interface controllers 34. TheDMA controller 62 is further coupled to the peripherals 32A-32C and the peripheralinterface controllers 34. In an embodiment, the DMA controller 62 and the CIF 58 maybe coupled to respective subsets of the peripherals 32A-32C and/or the peripheralinterface controllers 34. The subsets may overlap (e.g. some peripherals/peripheralinterface controllers may be configured to communicate with memory both throughDMA and through direct communications with the CIF 58). Otherperipherals/peripheral interface controllers may communicate with memory onlythrough DMA or only through operations directly transmitted to the CIF 58.
    [0035] The configuration registers 56A-56D may be programmed by software tocontrol various aspects of the operation of the cache control circuit 52 and thecoherence control circuit 54. Generally, circuit blocks may implement configurationregisters to permit software to select among various programmable configurations. Forexample, the size and configuration of the L2 cache 18 may be selectable within certainpredefined maximums. The writethrough/writeback operation of the cache may beconfigured. The coherence mode may be enabled and controlled through configurationregisters 56A-56D. In some embodiments, only the cache control circuit 52 mayinclude cache configuration registers 56A-56D or only the coherence control circuit 54may include cache configuration registers 56A-56D.
    [0036] If the L2 cache 18 is powered down, the configuration data stored in at leastsome of the configuration registers 56A-56D is lost. To restore the configuration aftera power down and subsequent power up of the L2 cache 18, the configuration data may be stored in the power up/power down memory 60. For example, when softwareprograms a configuration register 56A-56D with a value that is also to be restored onpower up, software may also write the value to the power up/power down memory 60.Similarly, there may be configuration register writes or other register writes to beperformed prior to power down. For example, a register may be written with asynchronization command to synchronize the L2 cache 18 (ensuring that anyoutstanding memory operations or other communications are complete) prior topowering down.
    [0037] The C1F 58 may be configured to read the operations from the power up/powerdown memory 60 during power up or power down events. The power manager 50 maybe configured to signal a power up or power down event to the CIF 58, and the C1F 58may be configured to read the memory 60 and transmit the operations for thecorresponding event to the L2 cache 18. Once the operations are complete, the CIF 58may be configured to communicate the completion to the power manager 50. Inresponse, the power manager 50 may complete the power up/power down event.
    [0038] Any communication may be implemented between the power manager 50 andthe CIF 58. In the illustrated embodiment, the power manager 50 may signal a powerup or power down event using the PwrUpReq signal. More specifically, the powermanager 50 may be configured to assert the PwrUpReq signal to indicate that the L2cache 18 is being powered up, and may be configured to deassert the PwrUpReq signalto indicate that the L2 cache 18 is being powered down. In response to the assertion ofthe PwrUpReq signal, the CIF 58 may be configured to read any operations in thepower up/power down memory 60 that are indicated as power up operations, and maybe configured to communicate the operations to the L2 cache 18. The CIF 58 may beconfigured to determine that the operations are complete (e.g. receiving writecompletions corresponding to each register write operation), and the CIF 58 may beconfigured to assert the PwrUpAck signal to acknowledge the power up event. Thepower manager 50 may be configured to re-enable communication to the L2 cache 18responsive to the assertion of the PwrUpAck signal.
    [0039] Powering down the L2 cache 18 may include at least powering down the cachecontrol circuit 52. In some embodiments, the coherence control circuit 54 may also bepowered down. The L2 cache memory 18B may remain powered on in someembodiments, retaining cache state in the cache (e.g. various cache blocks from thememory, state of the cache blocks such as tags, validity, and coherence state, etc.).Alternatively, the L2 cache memory 18B may also be powered down as part ofpowering down the L2 cache 18. Any circuitry/memory that was powered down maybe powered up again in response to a power up event.
    [0040] The power up/power down memory 60 may be formed from any semiconductorstorage. For example, multiple registers may be provided that may be read/written bysoftware. Other embodiments may use other forms of storage (e.g. random accessmemory (RAM) such as static RAM).
    [0041] The power up/power down memory 60 may generally include multiple entries.Two exemplary entries are illustrated in the memory 60 in Fig. 2. In the illustratedembodiment, each entry in the power up/power down memory 60 may include anaddress and data pair, illustrated as the A field and the Data field in the entries of Fig.
    2. The address may identify the configuration register to be written, and the data maybe the value to be written to the configuration register. The address may be relative(e.g. the address may be an offset from a base address corresponding to the L2 cachecontrol 18A, or base addresses for the coherence control circuit 54 and/or the cachecontrol circuit 52, more specifically). Alternatively, the address may be the full addressthat would be transmitted by the processor 16 in a write operation to the correspondingregister 56A-56D. Each entry may also include a valid bit (V) indicating whether ornot the entry is storing valid information. Additionally, in this embodiment, each entrymay include a power down (D) field which indicates whether the configuration registerwrite is performed during power down or during power up. The D bit in the D fieldmay be set to indicate a power down register write, and clear to indicate a power upregister write. Other embodiments may use different memories for power down andpower up, or may divide the memory in a known fashion, and the D field may not beincluded in each entry.
    [0042] In an embodiment, software may be expected to write the power downaddress/data pairs in the initial entries of the power up/power down memory 60 and towrite the power up address/data pairs in subsequent entries. In such an embodiment, inresponse to a power down event, the CIF 58 may read operations beginning with theinitial entry until an entry having the D bit cleared is encountered. The CIF 58 mayretain a pointer to the entry, and may begin reading power up operations from theindicated entry in response to a power up event (after which the pointer may be reset topoint to the initial entry again).
    [0043] While the power up/power down memory 60 may store configuration registerwrites, other embodiments may store any type of operations to be performed (e.g.register writes, register reads, commands, etc.). Accordingly, a flexible mechanism forpowering up and powering down the L2 cache 18 may be supported. The mechanismmay support powering the L2 cache 18 up or down while the processors 16 arepowered down (and without waking the processors 16). Additionally, because theoperations are programmable in the memory 60, the operations to be performed may bechanged and the order of the operations may be changed. Accordingly, the mechanismmay be corrected (if operating erroneously) via software changes even though themechanism itself operates in hardware.
    [0044] The cache control circuit 52 may generally be configured to manage access tothe L2 cache memory 18B. The cache control circuit 52 may detect hit/miss for cacheaccesses, initiate cache fills for misses, manage the replacement policy in the L2 cache18, etc. The coherence control circuit 54 may control cache coherence in the CPUblock 14 for processor 16 memory operations and for memory operations from the CIF58 (e.g. DMA operations from the DMA controller 62 and/or other memory operationsreceived directly from the peripherals 32A-32C and/or the peripheral interfacecontrollers 34). The coherence control 54 may maintain snoop tags for the caches inthe processors 16, and may also be configured to generate cache accesses to the cachecontrol circuit 52 to snoop the L2 cache memory 18B for cache coherence purposes.
    [0045] The power manager 50 may be configured to monitor the processors 16 and theL2 cache 18, as well as various other activity in the integrated circuit 10 (not shown in
    Fig. 2). The power manager 50 may control the power state of the processors 16,including power the processors 16 up or down, via the processor power control signals.The processors 16 may be powered up and down independently or in synchronizationin various embodiments.
    [0046] The power manager 50 may be configured to power down the L2 cache 18 aswell, if the L2 cache 18 is idle. The power manager 50 may detect that the L2 cache 18is idle in a variety of fashions. For example, the power manager 50 may be aware thatthe processors 16 are powered down, and thus no memory operations may be expectedfrom the processors 16. Additionally, the power manager 50 may detect that thebridge/DMA controller 30 is idle, at least with respect to memory operations. In theillustrated embodiment, the CIF 58 may generate an I/O idle signal. The CIF 58 mayassert the I/O idle signal to indicate that there are no memory operations pending fromthe peripherals 32A-32C and/or the peripheral interface controllers 34, including nomemory operations from the DMA controller 62. In an embodiment, the CIF 58 maydetect that there are no memory operations for a programmable number of consecutiveclock cycles before asserting the I/O idle signal to the power manager 50. In oneembodiment, if the CIF 58 has asserted the I/O idle signal and subsequently receives amemory operation, the CIF 58 may be configured to deassert the I/O idle signal.However, the CIF 58 may await an indication from the power manager 50 that thememory operations can be transmitted. The indication may avoid a race condition inwhich the power manager 50 has started a power down event prior to the receipt of thememory operation, and thus may prevent the transmission of the memory operation tothe L2 cache 18 where it could be lost as part of the power down event. In anembodiment, a ready signal (not shown) may be provided by the power manager 50 toindicate that the L2 cache 18 is ready for the memory operation after the assertion (anddeassertion) of the I/O idle signal.
    [0047] Turning next to Figs. 3-6, flowcharts are shown illustrating operation of oneembodiment of the power manager 50 and the CIF 58 for power up and power downevents for the L2 cache 18. While the blocks are shown in a particular order for ease ofunderstanding, other orders may be used. Blocks may be performed in parallel incombinatorial logic circuitry in the power manager 50 and/or the CIF 58. Blocks, combinations of blocks, and/or a flowchart as a whole may be pipelined over multipleclock cycles. The power manager 50 and/or the CIF 58 may be configured toimplement the operation illustrated in the flowchart. More particularly, the powermanager 50 and/or the CIF 58 may include hardware circuitry that implements theoperation illustrated.
    [0048] Fig. 3 is a flowchart illustrating operation of one embodiment of the powermanager 50 for a power down event. The power manager 50 may determine that apower down event is to occur if the processors 16 are powered down (decision block70, "yes" leg) and if the CIF 58 has signalled TO idle (decision block 72, "yes" leg). Ifso, the power manager 50 may deassert the PwrUpReq signal to the CIF 58 (block 74),initiating the power down event. The power manager 50 may await theacknowledgement from the CIF 58 (decision block 76), and in response to a deassertionof the PwrUpAck (decision block 76, "yes" leg), the power manager 50 may powerdown the L2 cache (block 78).
    [0049] Fig. 4 is a flowchart illustrating operation of one embodiment of the CIF 58 fora power down event. CIF 58 processing of the power down event may begin inresponse to deassertion of the PwrUpReq signal from the power manager 50 (decisionblock 80, "yes" leg). The CIF 58 may read an initial entry from the power up/powerdown memory 60 (block 82), and may determine if the entry is valid and is for a powerdown event (V and D set, decision block 84). If so (decision block 84, "yes" leg), theCIF 58 may transmit the address/data pair to the L2 control 18A to update the identifiedconfiguration register 56A-56D (block 86) and may read the next entry in the memory60 (block 82). If not (decision block 84, "no" leg), the CIF 58 may determine if thewrite responses for all of the configuration register writes have been received from theL2 control 18A (decision block 88). If the responses have been received (decisionblock 88, "yes" leg), the L2 control 18A may be prepared for power down and the CIF58 may deassert the PwrUpAck signal to acknowledge the power down request (block90).
    [0050] Fig. 5 is a flowchart illustrating operation of one embodiment of the powermanager 50 for a power up event. The power manager 50 may determine that a power up event is to occur if the processors 16 are to be powered up, or if a memory operationis received in the CIF 58 (causing the I/O idle to deassert). The power manager 50 maypower up the L2 cache control (block 100) and may wait for the power to stabilize.
    The power manager 50 may assert the PwrUpReq signal (block 102), and may wait forthe PwrUpAck signal to be asserted (decision block 104) to determine that the L2 cache18 is initialized and ready for communication again.
    [0051] Fig. 6 is a flowchart illustrating operation of one embodiment of the CIF 58 fora power up event. CIF 58 processing of the power up event may begin in response toassertion of the PwrUpReq signal (decision block 110, "yes" leg). The CIF 58 mayread the next entry in the power up/power down memory 60 (block 112). If the entry isvalid and a power up operation (V set and D clear, decision block 114, "yes" leg), theCIF 58 may transmit the configuration register write to the L2 cache control 18A(block 116) and may read the next entry in the memory 60 (block 112). If the entry isnot valid or is a power down operation (decision block 114, "no" leg), the CIF 58 maydetermine if the responses for the register writes have been received (decision block118). If so (decision block 118, "yes" leg), the CIF 58 may assert the PwrUpAck signal(block 120).
    [0052] In some embodiments, the power manager 50 may determine that the L2 cache18 is to power down during the processing of the power up event, or may determinethat the L2 cache 18 is to power up during the processing of the power down event. Insome implementations, the power manager 50 may be configured to permit the in¬progress transition to complete prior to initiating the new transition. In otherimplementations, the power manager 50 may be configured to signal the new transitionupon determination (e.g. by changing the state of the PwrUpReq signal). The CIF 58may be configured to monitor the PwrUpReq signal to detect the change of state, andmay cease processing the in-progress event. The CIF 58 may either be configured toacknowledge the changed state without further processing, or may process the newevent (performing the register writes for the new event).
    [0053] Fig. 7 is a timing diagram illustrating a power down and power up sequence forthe L2 cache 18, for one embodiment. Time may increase from left to right in Fig. 7, in arbitrary units. The L2 cache 18 may be powered up and operating at the beginning ofthe timing diagram (block 130), and the PwrUpReq and PwrUpAck signals are bothasserted. The power manager 50 may determine that the L2 cache is to be powereddown, and may deassert the PwrUpReq signal (dotted line 132). The CIF 58 may begintransmitting register writes and collecting responses (block 134). Once the writes arecomplete and the responses are received, the CIF 58 may deassert the PwrUpAck(dotted line 136) and the L2 cache 18 may be powered down (block 138). At a laterpoint, the power manager 50 may determine that the L2 cache 18 is to be powered up,and may assert the PwrUpReq signal after establishing power to the L2 cache 18(dotted line 140). The CIF 58 may transmit register writes to initialize theconfiguration registers (block 142), and may assert the PwrUpAck signal in response tocompleting the writes and receiving the responses (dotted line 144). The L2 cache 18may be powered up and operating again at this point (block 146).
    [0054] Turning now to Fig. 8, a flowchart is shown illustrating one embodiment ofsoftware that may update the L2 cache configuration. For example, the software mayinclude L2 configuration code that may execute during boot of the system 5 and/or atother times during operation of the system that the L2 cache configuration is changed.The L2 configuration code may be executed on one of the processors 16 to implementthe operation shown in Fig. 8. That is, the L2 configuration code may includeinstructions which, when executed by one of the processors 16, implements theoperation shown in Fig. 8. While the blocks are shown in a particular order for ease ofunderstanding, other orders may be used.
    [0055] The L2 configuration code may write one or more configuration registers in theL2 cache 18 (block 150). If one or more of the configuration registers also need to bewritten during a power down of the L2 cache 18 (decision block 152, "yes" leg), thecode may write the address of the configuration register and the corresponding data tothe power up/power down memory 60 (block 154). For example, a register write thatcauses a synchronization of the L2 cache 18 may be included. The code may set the Vand D bits in each entry written with a power down write. If one or more of theconfiguration registers are to be recovered during a power up of the L2 cache 18(decision block 156, "yes" leg), the code may write the address of the configuration register and the corresponding data to the power up/power down memory 60 and mayset the V bit and clear the D bit in each entry (block 158). It is noted that the sameconfiguration register may be included in both the power down writes and the power upwrites, in some embodiments.
    [0056] In another embodiment, the CIF 58 may be configured to detect writes toconfiguration registers 56A-56D (or subsets of the configuration registers that are to berestored on power up events and/or written on power down events). The CIF 58 mayautomatically capture the values written to the registers in the power up/power downmemory 60, and thus the L2 configuration code need not perform the writes to thememory 60 explicitly. In some such embodiments, the L2 configuration code may alsobe able to update the memory 60, in addition to the above-mentioned automaticcapture. The L2 configuration code may insert the synchronization command for powerdown events, for example.
    [0057] Turning next to Fig. 9, a block diagram of a computer accessible storagemedium 200 is shown. Generally speaking, a computer accessible storage mediummay include any storage media accessible by a computer during use to provideinstructions and/or data to the computer. For example, a computer accessible storagemedium may include storage media such as magnetic or optical media, e.g., disk (fixedor removable), tape, CD-ROM, or DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, orBlu-Ray. Storage media may further include volatile or non-volatile memory mediasuch as RAM (e.g. synchronous dynamic RAM (SDRAM), double data rate (DDR,DDR2, DDR3, etc.) SDRAM, low-power DDR (LPDDR2, etc.) SDRAM, RambusDRAM (RDRAM), static RAM (SRAM), etc.), ROM, Flash memory, non-volatilememory (e.g. Flash memory) accessible via a peripheral interface such as the UniversalSerial Bus (USB) interface, etc. Storage media may include microelectromechanicalsystems (MEMS), as well as storage media accessible via a communication mediumsuch as a network and/or a wireless link. The computer accessible storage medium 200in Fig. 9 may store L2 configuration code 202, which may implement the flowchart ofFig. 8. Generally, the computer accessible storage medium 200 may store any set ofinstructions which, when executed, implement a portion or all of the flowchart shown in Fig. 8. A carrier medium may include computer accessible storage media as well astransmission media such as wired or wireless transmission.
    [0058] Turning now to Fig. 10, a block diagram of one embodiment of a system 350 isshown. In the illustrated embodiment, the system 350 includes at least one instance ofan integrated circuit 10 coupled to an external memory 352. The external memory 352may form the main memory subsystem discussed above with regard to Fig. 1 (e.g. theexternal memory 352 may include the memory 12A-12B). The integrated circuit 10 iscoupled to one or more peripherals 354 and the external memory 352. A power supply356 is also provided which supplies the supply voltages to the integrated circuit 358 aswell as one or more supply voltages to the memory 352 and/or the peripherals 354. Insome embodiments, more than one instance of the integrated circuit 10 may beincluded (and more than one external memory 352 may be included as well).
    [0059] The memory 352 may be any type of memory, such as dynamic random accessmemory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2,DDR3, etc.) SDRAM (including mobile versions of the SDRAMs such as mDDR3,etc., and/or low power versions of the SDRAMs such as LPDDR2, etc.), RAMBUSDRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may becoupled onto a circuit board to form memory modules such as single inline memorymodules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, thedevices may be mounted with an integrated circuit 10 in a chip-on-chip configuration, apackage-on-package configuration, or a multi-chip module configuration.
    [0060] The peripherals 354 may include any desired circuitry, depending on the type ofsystem 350. For example, in one embodiment, the system 350 may be a mobile device(e.g. personal digital assistant (PDA), smart phone, etc.) and the peripherals 354 mayinclude devices for various types of wireless communication, such as wifi, Bluetooth,cellular, global positioning system, etc. The peripherals 354 may also includeadditional storage, including RAM storage, solid state storage, or disk storage. Theperipherals 354 may include user interface devices such as a display screen, includingtouch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, the system 350 may be any type ofcomputing system (e.g. desktop personal computer, laptop, workstation, net top etc.).
    [0061] Numerous variations and modifications will become apparent to those skilled inthe art once the above disclosure is fully appreciated. It is intended that the followingclaims be interpreted to embrace all such variations and modifications.
    权利要求:
    Claims (14)
    [1]
    An apparatus comprising: - a memory configured to store data identifying a first set of operations to be performed prior to turning off the operating voltage of a circuit block and a second setting operations to be performed after turning on the operating voltage of the circuit block; - a control circuit coupled to receive a request to switch off the operating voltage of the circuit block for a time when the operating voltage of processors in a system comprising the memory and the control circuit is switched off, the control circuit being configured to perform the corresponding first set operations identified in memory in response to the request.
    [2]
    The apparatus of claim 1, wherein the first set of operations comprises a first plurality of register write operations for a first plurality of registers in the circuit block, and wherein the data in the memory comprises a first plurality of addresses which the plurality of registers and a first plurality of to the first a plurality of registers to write data, and wherein the second set operations comprises a second plurality of register write operations for a second plurality of registers in the circuit block, and wherein the data in the memory comprises a second plurality of addresses which the second plurality of registers and a second plurality of data to be written to the second plurality of registers.
    [3]
    The apparatus of claim 2, wherein a first register is included in both the first plurality of registers and the second plurality of registers.
    [4]
    The device of claim 1, wherein the memory comprises one or more registers that are programmable by software with the first set operations and the second set of operations.
    [5]
    The apparatus of claim 1, wherein the control circuit is further configured to receive a request to turn on the operating power of a circuit block for a time when the operating power of the processors in the system is turned off, and wherein the control circuit is configured to perform the corresponding second set of operations identified in the memory in response to the request to turn on the operating power of the circuit block.
    [6]
    6. System comprising: - one or more processors; - the device according to claim 1, wherein the circuit block is a cache, which is coupled to the one or more processors; and - wherein the control circuit and the memory are included in a bridge that is coupled to the cache and is configured to be coupled to one or more peripheral devices, the memory comprising a plurality of registers that are programmable with data that the first set of operations and the represent second-set operations, and wherein the bridge is configured to perform the first set of operations in response to an operating power-off event for the cache and to perform the second set of operations in response to an operating power-up event for the cache.
    [7]
    The system of claim 6, further comprising a power controller configured to generate an operating power shutdown event in response to detecting that the operating power of the one or more processors is off, and further in response to detecting that no operations are going on from the one or more peripheral devices.
    [8]
    The system of claim 7, wherein the bridge is configured to acknowledge the operating power shut-off event in response to completion of the first plurality of operations.
    [9]
    The system of claim 7, wherein the power manager is configured to generate the operating power arming event, wherein the bridge is configured to acknowledge the operating power arming event in response to completing the second plurality of operations.
    [10]
    A method comprising: - detecting that the operating power of a circuit block should be switched on in a system comprising one or more processors coupled to the circuit block, the operating power of the one or more processors being switched off at the time of the detection; - issuing a request to a control circuit which is coupled to the circuit block and one or more peripheral devices; and - responding to the request by the control circuit by performing a plurality of operations stored in the control circuit to initialize one or more configuration registers in the circuit block.
    [11]
    The method of claim 10, wherein each operation is represented by an address of the configuration register and a value to be written to the configuration register.
    [12]
    The method of claim 10, further comprising: - detecting that the operating power of the circuit block should be turned off; - issuing a second request to the control circuit; and - responding to the second request by the control circuit by performing one or more second operations stored in the control circuit.
    [13]
    The method of claim 12, wherein the one or more second operations cause a synchronization operation in the circuit block.
    [14]
    The method of claim 12, further comprising: - determining by the control circuit that the one or more second operations are complete; - the control circuit confirming the second request in response to the determination; and - switching off the operating power of the circuit block in response to confirmation by the bridge.
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    法律状态:
    优先权:
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    US89451610|2010-09-30|
    US12/894,516|US8806232B2|2010-09-30|2010-09-30|Systems and method for hardware dynamic cache power management via bridge and power manager|
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